The present application contains subject matter related to a concurrently filed U.S. Patent Application by Ramkumar Subramanian, Wenge Yang, Marina V. Plat, and Lewis Shen entitled xe2x80x9cSEMICONDUCTOR MANUFACTURING METHOD USING A DIELECTRIC PHOTOMASKxe2x80x9d. The related application is assigned to Advanced Micro Devices, Inc. and is identified by docket number D961.
The present application contains subject matter related to a concurrently filed U.S. Patent Application by Ramkumar Subramanian, Minh Van Ngo, Suzette K. Pangrle, and Kashmir S. Sahota entitled xe2x80x9cSEMICONDUCTOR MANUFACTURING METHOD USING A HIGH EXTINCTION COEFFICIENT DIELECTRIC PHOTOMASKxe2x80x9d. The related application is assigned to Advanced Micro Devices, Inc. and is identified by docket number D962.
The present application also contains subject matter related to a concurrently filed U.S. Patent Application by Ramkumar Subramanian, Minh Van Ngo, Suzette K. Pangrle, Kashmir S. Sahota, and Christopher F. Lyons entitled xe2x80x9cMETHOD FOR CREATING PARTIALLY UV TRANSPARENT ANTI-REFLECTIVE COATING FOR SEMICONDUCTORSxe2x80x9d. The related application is assigned to Advanced Micro Devices, Inc. and is identified by docket number D963.
The present application also contains subject matter related to a concurrently filed U.S. Patent Application by Ramkumar Subramanian, Minh Van Ngo, Kashmir S. Sahota, YongZhong Hu, Hiroyuki Kinoshita, Fei Wang, and Wenge Yang entitled xe2x80x9cMETHOD FOR ELIMINATING ANTI-REFLECTIVE COATING IN SEMICONDUCTORSxe2x80x9d. The related application is assigned to Advanced Micro Devices, Inc. and is identified by docket number D971.
The present invention relates generally to memory devices and more particularly to a method for creating an anti-reflective coating that does not have to be removed.
Memory devices, such as a Flash electrically erasable programmable read only memory (EEPROM), are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a xe2x80x9cstacked gatexe2x80x9d structure or word line. The stacked gate structure typically includes: a thin gate dielectric layer or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric layer overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as xe2x80x9ccontactsxe2x80x9d, must be made to connect the stack gated structure, the source region and the drain regions to other part of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch-stop layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide, is then deposited over the nitride layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings. The contact openings stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called xe2x80x9cself-aligned contactsxe2x80x9d (conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
As semiconductor devices have shrunk in size, the industry has turned towards deep ultraviolet (DUV) lithography as a photolithographic process to pattern contact openings in sub-0.35 micron line geometry semiconductor devices.
A major obstacle to the miniaturization of semiconductors is the effect of reflectivity in the DUV lithographic and conventional i-line lithographic processes. Reflections occur at the junctions of materials and are influenced in part by the thickness of materials. Because the precision of the photolithographic process is sensitive to such reflections, reducing the reflections by lowering the reflectivity of materials under about 15% is essential. In particular, the differences in thickness caused by the polysilicon, metal, and poly/metal stacks has made small feature patterning and critical dimension (CD) control of photoresist very difficult. Such topography causes unpredictable swings in material reflectivity and needs to be reduced or dampened in some way in order to reduce semiconductor device size. Non-uniformities occurring when the dielectric layer undergoes CMP can increase the total reflectivity from the dielectric to the photoresist during photolithography and cause further disruptions in patterning.
To solve this problem, different anti-reflective coatings (ARCs) have been developed which work by phase shift cancellation of specific wavelengths to provide uniform resist patterning. Top anti-reflective coatings (TARCs) are placed on top of the photoresist and are specifically designed so that the reflective light from the resist/ARC interface is equal in amplitude but opposite in phase to the light reflected from the ARC/reflective layer interface.
It has been found that there are certain line width variations which are due to the ARC not being able to reduce the reflective layer reflectivity to a minimum. The reflectivity causes problems with the resist which have been corrected in part by the use of bottom anti-reflective coatings (BARCs) located under the resists.
Silicon oxynitride (SiON) by itself has been found to be a good BARC material. In essence, the silicon oxynitride BARC serves two functions during semiconductor memory manufacturing: (1) as a hard mask during self-aligned etch (SAE) and during self-aligned-source etch; and (2) as a bottom anti-reflective layer for photolithography at second gate masking. In order for the silicon oxynitride to act as an adequate hard mask, it must be approximately 100 nm thick in current applications. However, the ideal BARC thickness is approximately 30 nm, which is not thick enough to survive the SAE and self-aligned source etching processes. Thus, a 100 nm silicon oxynitride BARC is currently required and this causes line widths to be non-uniform. The non-uniform line width is a result of lensing reflections of light into the photoresist from undulations in the topography of reflective layers under the BARC that are not completely phase cancelled by the BARC.
One significant problem with ARCs is that they are not transparent to the ultra-violet light normally used when erasing Flash memories. While this is not a problem in most non-memory semiconductor devices, in this case, the BARC layer must be removed as an added step to the creation process.
The BARC layer is often removed anyways because, left in, the BARC layer would also create capacitance between the contacts because of its relatively high dielectric constant and would greatly reduce the transistor switching speed. This would add to the adverse speed impact which increases disproportionately with shortened channels. Basically, the parasitic capacitance due to lightly doped drain (LDD) structures as a percentage of the total transistor capacitance is higher for sub-0.18 micron transistors than it is for a 0.18 micron transistor and even worse for a sub-0.13 transistor, making the overall adverse speed impact much more severe in smaller transistors.
Although removal of the ARC is necessary for the above reasons, the actual removal process causes problems. The most significant problem is the cost and complexity in adding ARC removal steps.
Attempts have been made to develop a thin photoresist layer which would allow for the removal of ARC layers as a byproduct of existing etching steps, thus avoiding the additional cost of and complexity. However, it is extremely difficult to deposit and polish a sufficiently thin layer of defect-free photoresist.
Another problem is that the CMP that is used in the removal process of the BARC layer inherently removes portions of the conductive contacts as well as the dielectric layer, producing deep scratches therein. The scratches vary significantly from memory cell to memory cell, creating non-uniformity and adversely affecting device performance.
Rather than use CMP, attempts have been made to develop an etch chemistry that is more selective so that the ARC would be etched at a much higher rate than the conductive contacts and the dielectric layer. Unfortunately, these attempts have been unsuccessful.
A solution, which would provide an ARC layer of sufficient thickness to act as a mask, produce the uniform line width required as semiconductors are reduced in size, and eliminate the scratching of the dielectric layer associated with the removal of the BARC, has long been sought but has eluded those skilled in the art. As miniaturization continues at a rapid pace in the field of semiconductors, it is becoming more pressing that a solution be found.
The present invention provides a method of manufacturing a semiconductor device by forming a plurality of semiconductor devices on a semiconductor substrate. A dielectric layer is then deposited and polished to form a planar surface. Then, an ARC layer of low dielectric constant is deposited and a layer of photoresist for patterning contacts and local interconnects (LI) on the low dielectric constant layer is deposited. The low dielectric constant layer is then etched to form contacts and LI. Thus, the method provides an anti-reflective coating (ARC) for a semiconductor device that does not need to be removed.
The present invention further provides a method of manufacturing a semiconductor device with an optically transparent ARC at UV wavelengths commonly used in DUV lithography.
The present invention further provides a method of manufacturing a semiconductor device with an ARC with a low dielectric constant. Since a material with low dielectric constant would not increase the capacitance between contacts, such an ARC eliminates the need for a removal step.
The present invention further provides a method of manufacturing a semiconductor device with an ARC with optimized optical constants which can reduce the reflectivity from a reflective layer at a particular wavelength towards zero while, at the same time, being adequately thick to serve as a mask for etch.
The present invention further provides a method of manufacturing a semiconductor device with an ARC composed of a low dielectric material such as HSQ, BCB, Flare, or Silk. Because such low dielectric materials are optically transparent at the DUV wavelengths being used (248 nm), the thickness of the ARC can be chosen to be adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch and, at the same time, to satisfy an under 15% reflectivity requirement.